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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad7302 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 2.7 v to 5.5 v, parallel input dual voltage output 8-bit dac functional block diagram power on reset cs wr d0 refin v dd ad7302 v out a dgnd d7 agnd a /b clr ldac pd i/v v out b mux ? 2 input register dac register i dac a dac register i dac b i/v input register control logic features two 8-bit dacs in one package 20-lead dip/soic/tssop package +2.7 v to +5.5 v operation internal and external reference capability dac power-down function parallel interface on-chip output buffer rail-to-rail operation low power operation 3 ma max @ 3.3 v power-down to 1 m a max @ 25 8 c applications portable battery powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators general description the ad7302 is a dual, 8-bit voltage out dac that operates from a single +2.7 v to +5.5 v supply. its on-chip precision output bu ffers allow the dac outputs to swing rail to rail. the ad7302 has a parallel microprocessor and dsp-compatible interface with high speed registers and double buffered interface logic. data is loaded to the registers on the rising edge of cs or wr and the a /b pin selects either dac a or dac b. reference selection for ad7302 can be either an internal reference derived from the v dd or an external reference applied at the refin pin. both dacs can be simultaneously updated using the asynchronous ldac input and can be cleared by using the asynchronous clr input. the low power consumption of this part makes it ideally suited to portable battery operated equipment. the power consump- tion is less than 10 mw at 3.3 v, reducing to 3 m w in power- down mode. the ad7302 is available in a 20-pin plastic dual-in-line package, 20-lead soic and a 20-lead tssop package. product highlights 1. low power, single supply operation. this part operates from a single +2.7 v to +5.5 v supply and typically consumes 15 mw at 5 v, making it ideal for battery powered applications. 2. the on-chip output buffer amplifiers allow the outputs of the dacs to swing rail to rail with a settling time of typically 1.2 m s. 3. internal or external reference capability. 4. high speed parallel interface. 5. power-down capability. when powered down the dac consumes less than 1 m a at 25 c. 6. packaged in 20-lead dip, soic and tssop packages.
C2C rev. 0 ad7302Cspecifications (v dd = +2.7 v to +5.5 v, internal reference; c l = 100 pf, r l = 10 k v to v dd and gnd; to t max unless otherwise noted) parameter b versions 1 units conditions/comments static performance resolution 8 bits relative accuracy 1 lsb max note 2 differential nonlinearity 1 lsb max guaranteed monotonic full-scale error C0.75 lsb typ zero code error @ 25 c 3 lsb typ all zeroes loaded to dac register gain error 3 1 % fsr typ zero code temperature coefficient 100 m v/ c typ dac reference input refin input range 1.0 to v dd /2 v min to max refin input impedance 10 m w typ output characteristics output voltage range 0 to v dd v min to max output voltage settling time 2 m s max typically 1.2 m s slew rate 7.5 v/ m s typ digital to analog glitch impulse 1 nv-s typ 1 lsb change around major carry digital feedthrough 0.2 nv-s typ digital crosstalk 0.2 nv-s typ analog crosstalk 0.2 lsb typ dc output impedance 40 w typ short circuit current 14 ma typ power supply rejection ratio 4 0.0003 %/% max d v dd = 10% logic inputs input current 10 m a max v inl , input low voltage 0.8 v max v dd = +5 v v inl , input low voltage 0.6 v max v dd = +3 v v inh , input high voltage 2.4 v min v dd = +5 v v inh , input high voltage 2.1 v min v dd = +3 v pin capacitance 7 pf max power requirements v dd 2.7/5.5 v min/max i dd both dacs active and excluding load currents v dd = 3.3 v v ih = v dd and v il = gnd @ 25 c 2.8 ma max typically 2.3 ma @ t min to t max 3 ma max see figures 6 and 7 v dd = 5.5 v v ih = v dd and v il = gnd @ 25 c 4.5 ma max typically 2.8 ma @ t min to t max 5 ma max see figures 6 and 7 i dd (full power-down) @ 25 c1 m a max v ih = v dd and v il = gnd t min to t max 2 m a max see figure 18 notes 1 temperature ranges are as follows: b version: C40 c to +105 c. 2 relative accuracy is calculated using a reduced code range of 15 to 245. 3 gain error is specified between codes 15 and 245. the actual error at code 15 is typically 3 lsb. 4 guaranteed by characterization at product release, not production tested. specifications subject to change without notice.
ad7302 C3C rev. 0 timing characteristics 1, 2 limit at t min , t max parameter (b version) units conditions/comments t 1 0 ns min address to write setup time t 2 0 ns min address valid to write hold time t 3 0 ns min chip select to write setup time t 4 0 ns min chip select to write hold time t 5 20 ns min write pulse width t 6 15 ns min data setup time t 7 4.5 ns min data hold time t 8 20 ns min write to ldac setup time t 9 20 ns min ldac pulse width t 10 20 ns min clr pulse width notes 1 sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. tr and tf should not exceed 1 m s on any digital input. 2 see figure 1. a /b cs wr d7?0 ldac clr t 1 t 2 t 4 t 3 t 5 t 6 t 7 t 8 t 10 t 9 figure 1. timing diagram for parallel data write (v dd = +2.7 v to +5.5 v; gnd = 0 v; reference = internal v dd /2 reference; all specifications t min to t max unless otherwise noted)
ad7302 C4C rev. 0 ordering guide temperature package model range options* ad7302bn C40 c to +105 c n-20 ad7302br C40 c to +105 c r-20 ad7302bru C40 c to +105 c ru-20 *n = plastic dip; r = small outline; ru =thin shrink small outline. absolute maximum ratings* (t a = +25 c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v reference input voltage to agnd . . . .C0.3 v to v dd + 0.3 v digital input voltage to dgnd . . . . . C0.3 v to v dd + 0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, 0.3 v v out a, v out b to agnd . . . . . . . . . . . . C0.3 v, v dd + 0.3 v operating temperature range commercial (b version) . . . . . . . . . . . . . C40 c to +105 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150 c plastic dip package, power dissipation . . . . . . . . . . 900 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 102 c/w lead temperature (soldering, 10 sec) . . . . . . . . . . . +260 c tssop package, power dissipation . . . . . . . . . . . . . 700 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 143 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220 c soic package, power dissipation . . . . . . . . . . . . . . . 870 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 74 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7302 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7302 C5C rev. 0 pin function descriptions pin no. mnemonic function 1-8 d7Cd0 parallel d ata inputs. eight-bit data is loaded to the input register of the ad7302 under the control of cs and wr . 9 cs chip select. active low logic input. 10 wr write input. wr is an active low logic input used in conjunction with cs and a /b to write data to the selected dac register. 11 a /b dac select. address pin used to select writing to either dac a or dac b. 12 pd active low input used to put the part into low power mode reducing current consumption to less than 1 m a. 13 ldac load dac logic input. when this logic input is taken low both dac outputs are simultaneously updated with the contents of their dac registers. if ldac is permanently tied low, the dacs are updated on the rising edge of wr . 14 clr asynchronous clear input (active low). when this input is taken low the dac registers are loaded with all zeroes and the dac outputs are cleared to zero volts. 15 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v and should be decoupled to agnd. 16 refin external reference input. this can used as the reference for both dacs. the range on this reference input is 1 v to v dd /2. if refin is directly tied to v dd the internal v dd /2 reference is selected. 17 agnd analog ground reference point and return point for all analog current on the part. 18 v out b analog output voltage from dac b. the output amplifier can swing rail to rail on its output. 19 v out a analog output voltage from dac a. the output amplifier can swing rail to rail on its output. 20 dgnd digital ground reference point and return point for all digital current on the part. pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ad7302 (msb) db7 agnd v out b v out a dgnd db6 db5 db4 clr v dd refin db3 db2 db1 (lsb) db0 cs wr a /b pd ldac
ad7302 C6C rev. 0 terminology integral nonlinearity for the dacs, relative accuracy or endpoint nonlinearity is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a graphical representation of the transfer curve is shown in figure 14. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero code error zero code error is the measured output voltage from v out of either dac when zero code (all zeros) is loaded to the dac latch. it is due to a combination of the offset errors in the dac and output amplifier. zero scale error is expressed in lsbs. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal, expressed as a percent of the full-scale value. it includes full-scale errors but not offset errors. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the digital inputs change state with the dac selected and the ldac used to update the dac. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital inputs of the same dac, but is measured when the dac is not updated. it is specified in nv-s and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one converter due to a digital code change to another dac. it is specified in nv-s. analog crosstalk analog crosstalk is a change in output of any dac in response to a change in the output of the other dac. it is measured in lsbs. power supply rejection ratio (psrr) this specification indicates how the output of the dac is affected by changes in the power supply voltage. power supply rejection ratio is quoted in terms of % change in output per % change in v dd for full-scale output of the dac. v dd is varied 10%.
typical performance characteristicsC ad7302 sink current ?ma v out ?mv 800 0 08 24 6 720 400 240 160 80 640 560 320 480 v dd = 5v and 3v internal reference t a = +25
ad7302 C8C rev. 0 1
ad7302 C9C rev. 0 general description d/a section the ad7302 is a dual 8-bit voltage output digital-to-analog converter. the architecture consists of a reference amplifier, a current source dac followed by a current-to-voltage converter capable of generating rail-to-rail voltages on the output of the dac. figure 19 shows a block diagram of the basic dac architecture. reference amplifier + - v o a/b v dd refin ad7302 current dac i/v 30k w 30k w 11.7k w 11.7k w figure 19. dac architecture both dac a and dac b outputs are internally buffered and these output buffer amplifiers have rail-to-rail output character- istics. the output amplifier is capable driving a load of 10 k w to both v dd and ground in parallel with a 100 pf to ground. the reference selection for the dac can either be internally generated from v dd or externally applied through the refin pin. a comparator on the refin pin detects whether the required reference is the internally generated reference or the externally applied voltage to the refin pin. if refin is connected to v dd , the reference selected is the internally generated v dd /2 reference. when an externally applied voltage is more than one volt below v dd , the comparator selection switches to the externally applied voltage to the refin pin. the range on the external reference input is from 1.0 v to v dd /2. the output voltage from either dac is given by: v o a/b = 2 v ref ( n /256) where: v ref is the voltage applied to the external refin pin or v dd /2 when the internal reference is selected. n is the decimal equivalent of the code loaded to the dac register and ranges from 0 to 255. reference the ad7302 has the facility to use either an external reference applied through the refin pin or an internal reference generated from v dd . figure 20 shows the reference input arrangement where either the internal v dd /2 reference or the externally applied reference can be selected. comparator vth pmos mux int ref selected reference output v dd ref in int ref ext ref figure 20. reference selection circuitry the internal reference is selected by tying the refin pin to v dd . if an external reference is to be used, this can be directly applied to the refin pin; if this is 1 v below v dd , the internal circuitry will select this externally applied reference as the reference source for the dac. digital interface the ad7302 contains a fast parallel interface allowing this dual dac to interface to industry standard microprocessors, micro- contr ollers and dsp machines. there are two modes in which this parallel interface can be configured to update the dac outputs. the simultaneous update mode allows simultaneous updating of both dac outputs. the automatic update mode allows each dac to be individually updated following a write cycle. figure 21 shows the internal logic associated with the digital interface. the pon strb signal is internally generated from the power on reset circuitry and is low during the power- on reset phase of the power-up procedure. clr pon strb ldac a /b cs wr clear ldac dac a sel dac a control logic enable set sle mle a sle a clr clear ldac dac b sel dac b control logic enable set sle mle b sle b figure 21. logic interface the ad7302 has a double buffered interface, which allows for simultaneous updating of the dac outputs. figure 22 shows a block diagram of the register arrangement within the ad7302. db7?b0 input register lower nibble 4 to 15 decoder dac register drivers 4 15 15 30 8 upper nibble 4 to 15 decoder dac register drivers 4 15 15 30 control logic sle mle a /b cs wr ldac clr figure 22. register arrangement
ad7302 C10C rev. 0 automatic update mode in this mode of operation the ldac signal is permanently tied low. the state of the ldac is sampled on the rising edge of wr . ldac being low allows the selected dac register to be automatically updated on the rising edge of wr . the output update occurs on the rising edge of wr . figure 23 shows the timing associated with the automatic update mode of operation and also the status of the various registers during this frame. a /b cs wr d7?0 ldac = 0 hold hold track i/p reg (mle) track hold dac reg (sle) track v out figure 23. timing and register arrangement for auto- matic update mode simultaneous update mode in this mode of operation the ldac signal is used to update both dac outputs simultaneously. the state of the ldac is sampled on the rising edge of wr . if ldac is high, the automatic update mode is disabled and both dac latches are updated at any time after the write by taking ldac low. the output update occurs on the falling edge of ldac . ldac must be taken back high again before the next data tran sfer takes place. figure 24 shows the timing associated with the simultaneous update mode of operation and also the status of the various registers during this frame. a /b cs wr d7?0 ldac hold hold track i/p reg (mle) track hold dac reg (sle) v out hold figure 24. timing and register arrangement for simulta- neous update mode power-on reset the ad7302 has a power-on reset circuit designed to allow output stability during power-up. this circuit holds the dacs in a reset state until a write takes place to the dac. in the reset state all zeros are latched into the input registers of each dac and the dac registers are in transparent mode, thus the output of both dacs is held at ground potential until a write takes place to the dac. the power-on reset circuitry generates a pon strb signal, which is a gating signal used within the logic to identify a power-on condition. power-down features the ad7302 has a power-down feature. this is implemented by exercising the external pd pin; an active low signal puts the complete dac into power-down mode. when in power-down the current consumption of the device is reduced to 1 m a max at 25 c and 2 m a max over temperature, making the device suitable for use in portable battery powered equipment. when power-down is activated, the reference bias servo loop and the output amplifiers with their associated linear circuitry are powered down, the refer ence resistors are open circuited to further reduce the power consumption. the output sees a load of approximately 23 k w to gnd when in power-down mode as shown in figure 25. the contents of the data registers are unaffected when in power-down mode. the device comes out of power-down in typically 13 m s (see figure 10). i dac 11.7k w 11.7k w v ref v dd figure 25. output stage during power-down analog outputs the ad7302 contains two independent voltage output dacs with 8-bit resolution and rail-to-rail operation. the output buffer provides a gain of two at the output. figures 2 to 4 s how the source and sink capabilities of the output a mplifier. the slew rate of the output amplifier is typically 7.5 v/ m s and has a full- scale settling to 8 bits with a 100 pf capacitive load in typically 1.2 m s. the input coding to the dac is straight binary. table i shows the binary transfer function for the ad7302. figure 26 shows the dac transfer function for binary coding. any dac output voltage can be expressed as: v out = 2 v ref ( n /256) where: n is the decimal equivalent of the binary input code. n ranges from 0 to 255.
ad7302 C11C rev. 0 v ref is the voltage applied to the external refin pin when the external reference is selected and is v dd /2 if the internal reference is used. table i. output voltage for selected input codes digital input msb . . . lsb analog output 1111 1111 2 255/256 v ref v 1111 1110 2 254/256 v ref v 1000 0001 2 129/256 v ref v 1000 0000 v ref v 0111 1111 2 127/256 v ref v 0000 0001 2 v ref /256 v 0000 0000 0 v 00 01 dac input code ff 80 81 fe 7f 0 2.v ref v ref dac output voltage figure 26. dac transfer function figure 27 shows a typical setup for the ad7302 when using its internal reference. the internal reference is selected by tying the refin pin to v dd . internally in the reference section there is a reference detect circuit that will select the internal v dd /2 based on the voltage connected to the refin pin. if refin is within a threshold voltage of a pmos device (approximately 1 v) of v dd the internal reference is selected. when the refin voltage is more than 1 v below v dd , the externally applied voltage at this pin is used as the reference for the dac. the internal reference on the ad7302 is v dd /2, the output current to voltage converter within the ad7302 provides a gain of two. thus the output range of the dac is from 0 v to v dd , based on table i. ad7302 v out a v out b 10? 0.1? v dd = 3 to 5v v dd a/b ref in clr pd v dd agnd dgnd cs wr ldac d7?0 v out a v out b data bus control inputs figure 27. typical configuration selecting the internal reference figure 28 shows a typical setup for the ad7302 when using an external reference. the reference range for the ad7302 is from 1 v to v dd /2 v. higher values of reference can be incorporated, but will saturate the output at both the top and bottom end of the transfer function. there is a gain of two from input to output on the ad7302. suitable references for 5 v operation are the ad780 and ref192. for 3 v operation a suitable external reference would be the ad589 a 1.23 v bandgap reference. ad7302 v out a v out b 10? 0.1? v dd = 3 to 5v v dd ad780/ref192 with v dd = 5v or ad589 with v dd = 3v ref in gnd v out v in 0.1? ext ref v dd agnd dgnd d7?0 v out a v out b data bus control inputs a/b clr pd cs wr ldac figure 28. typical configuration using an external reference
ad7302 C12C rev. 0 microprocessor interfacing ad7302Cadsp-2101/adsp-2103 interface figure 29 shows an interface between the ad7302 and the adsp-2101/adsp-2103. the fast interface timing associated with the ad7302 allows easy interface to the adsp-2101/ adsp-2103. addr decode data bus address bus cs db0 db7 ad7302* a /b dma0 dma14 wr en dmd0 dmd15 adsp-2101*/ adsp-2103* wr dms a** a+1** * *additional circuitry omitted for clarity. **a decoded address for dac a. ** a+1 decoded address for dac b. ldac figure 29. ad7302Cadsp-2101/adsp-2103 interface two addresses are decoded to select loading data to either dac a or dac b. ldac is permanently tied low in this circuit, so the selected dac output is updated on the rising edge of the wr signal. data is loaded to the ad7302 input register using the following adsp-21xx instruction: dm ( dac ) = mr0 mr0 = adsp-21xx mr0 register. dac = decoded dac address. ad7302Ctms32020 interface figure 30 shows an interface between the ad7302 and the tms32020. the address decoder is used to decode the addresses for dac a and dac b. data is loaded to the ad7302 using the following instruction: out dac, d dac = decoded dac address. d = data memory address. addr decode data bus address bus cs db0 db7 ad7302* a /b a0 a15 strb en dmd0 dmd15 tms32020 wr is a** a+1** * *additional circuitry omitted for clarity. **a decoded address for dac a. ** a+1 decoded address for dac b. ldac r/ w figure 30. ad7302Ctms32020 interface in the circuit shown the ldac is hardwired low, thus the selected dac output is updated on the rising edge of wr . some applications may require simultaneous updating of both dacs in the ad7302. in this case the ldac signal can be driven from an external timer or can be controlled by the microprocessor. one option for simultaneous updating is to decode the ldac from the address bus so that a write opera- tion at this address will simultaneously update both dac outputs. a simple or gate with one input driven from the decoded address and the second input from the wr signal will implement this function. ad7302C8051/8088 interface figure 31 shows a serial interface between the ad7302 and the 8051/8088 processors. the address decoder is used to decode the addresses for dac a and dac b. addr decode address/data bus address bus
ad7302 C13C rev. 0 applications bipolar operation using the ad7302 the ad7302 has been designed for single supply operation, but bipolar operation is achievable using the circuit shown in figure 32. the circuit shown has been configured to achieve an output voltage range of C5 v < v o < +5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or op295 as the output amplifier. the output voltage for any input code can be calculated as follows: v o = [(1 +r 4 /r 3) ( r 2 / ( r 1 +r 2) (2 v ref d/ 256 ) ] C r 4 v ref /r3 where d is the decimal equivalent of the code loaded to the dac and v ref is the reference voltage input. with v ref = 2.5 v, r1 = r3 = 10 k w and r2 = r4 = 20 k w and v dd = 5 v. v out = (10 d /256) C 5 v ad7302 v out a 10? 0.1? v dd = 5v v dd agnd ad780/ref192 with v dd = 5v or ad589 with v dd = 3v ref in gnd v out v in 0.1? ext ref r1 10k w r2 20k w r4 20k w r3 10k w +5v ?v 5v dgnd ad820/ op295 figure 32. bipolar operation using the ad7302 decoding multiple ad7302 in a system the cs pin on the ad7302 can be used in applications to decode a number of dacs. in this application all dacs in the system receive the same input data, but only the cs to one of the dacs will be active at any one time allowing access to two channels in the system. the 74hc139 is used as a two-to-four line decoder to address any of the dacs in the system. to prevent t iming errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing st ate. figure 33 shows a diagram of a typical setup for decoding multiple ad7302 devices in a system. the built-in power-on reset circuit on the ad7302 ensures that the outputs of all dacs in the system power up with zero volts on their outputs. ad7302
ad7302 C14C rev. 0 programmable current source figure 35 shows the ad7302 used as the control element of a programmable current source. in this circuit the full-scale current is set to 1 ma. the output voltage from the dac is applied across the current setting resistor of 4.7 k w in series with the full-scale setting resistor of 470 w . transistors suitable to place in the feedback loop of the amplifier include the bc107 or the 2n3904, which enable the current source to operate from a min v source of 6 v. the operating range is determined by the ope rating characteristics of the of the transistor. suitable amplifiers include the ad820 and the op295 both having rail- to-rail operation on their outputs. the current for any digital input code can be calculated as follows: i = 2 v ref d/ (5 e + 3 256) ma ad7302 v out a 10? 0.1? v dd = 5v v dd agnd ad780/ref192 with v dd = 5v ref in gnd v out v in 0.1? ext ref 4.7k w 470 w +5v load v source ad820/ op295 dgnd figure 35. programmable current source coarse and fine adjustment using the ad7302 the dacs on the ad7302 can be paired together to form a coarse and fine adjustment function as shown in figure 36. in this circuit dac a is used to provide the coarse function while dac b is used to provide the fine adjustment. varying the ratio of r1 and r2 will vary the relative effect of the coarse and fine tune elements in the circuit. for the resistor values shown dac b has a resolution of 148 m v giving a fine tune range of approximately 2 lsbs for operation with a v dd of 5 v and a reference of 2.5 v. the amplifiers shown allow a rail-to-rail output voltage to be achieved on the output. a typical applica- tion for such a circuit would be in a setpoint controller. ad7302 v out a 10? 0.1? v dd = 5v v dd agnd ad780/ref192 with v dd = 5v or ad589 with v dd = 3v ref in gnd v out v in 0.1? ext ref r2 51.2k w r4 390 w r1 390 w +5v v out dgnd ad820/ op295 v out b r3 51.2k w figure 36. coarse/fine adjust circuit power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad7302 is mounted should be designed so the analog and digital sections are separated and confined to certain areas of the board. if the ad7302 is in a system where multiple devices require an agnd to dgnd connection, the connection should be made at one point only, a star ground point that should be established as closely as possible to the ad7302. the a d7302 should have ample supply bypassing of 10 m f in parallel with 0.1 m f on the supply located as close to the package as possible, ideally right up against the device. the 10 m f capacitors are the tantalum bead type. the 0.1 m f capaci tor should have low effective series resistance (esr) and effective series induc- tance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad7302 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching sig- nals like clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feed- through through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
ad7302 C15C rev. 0 20-lead plastic dip (n-20) 20 110 11 1.060 (26.90) 0.925 (23.50) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 20-lead so (r-20) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 20 11 10 1 0.5118 (13.00) 0.4961 (12.60) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 20-lead tssop (ru-20) 20 11 10 1 0.260 (6.60) 0.252 (6.40) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 outline dimensions dimensions shown in inches and (mm).
C16C c2990C12C4/97 printed in u.s.a.

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